It is often a goal of electronic designers to design circuits that utilize a low supply voltage and/or consume a minimum amount of power. This may particularly be the case for Analog to Digital Converters (ADC).
Various known techniques may reduce the high power consumption common to many ADC devices. Such techniques include a Pulse Modulation ADC using irregular sampling, as disclosed in United States Patent Application US 2009/0091486 A1, to Wiesbauer et al., which is incorporated herein in its entirety.
A contemporary Pulse Modulation ADC converts a continuous time analog signal into a discrete time digital signal. The Pulse Modulation ADC is primarily composed of a modulator and a measurement engine, and generally includes a demodulator or other digital signal processor. The Sigma-Delta configuration of the modulator of the contemporary Pulse Modulation ADC is characterized by the inclusion of active elements. Specifically, the modulator of the Pulse Modulation ADC generally includes an operational amplifier or operational transconductance amplifier acting as an integrator.
As the frequency of operation increases, the behavior of the active integrator becomes less ideal, and so the benefit (the linear response) of using an active element such as an operational amplifier in a summation function is generally lost, and the disadvantages to using the active element (increase in size and power consumption to maintain acceptable performance characteristics) become more apparent. Therefore, the Pulse Modulation ADC may still require a higher than desired supply voltage, and consume relatively more power, in addition to requiring greater circuit area. Any increase in the consumption of power and circuit area is usually not desirable, especially in implementations performed with 100 nm technology or smaller.